Single cable demodulator with Out-Of Band receiver

TDA10026HN 1. General description The TDA10026HN is a Single Cable Downstream Processor. The Cable Downstream Processor (CDP) implements

13-bit 1 : 2 SSTL_2 registered buffer for DDR

SSTVF16859 1. General description The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate

14-bit SSTL_2 registered driver with differential clock inputs

SSTV16857 SSTV16857 14-bit SSTL_2 registered driver with differential clock inputs Product data Supersedes data

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programmable output for DDR2-800 RDIMMs

SSTUP32866 1. General description The SSTUP32866 is a 1.8 V configurable

1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

SSTUM32868 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed

1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applications

SSTUH32865 1. General description The SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register

1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications

SSTUH32864 1. General description The SSTUH32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer

1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

SSTUB32868 1. General description The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

SSTUB32866 1. General description The SSTUB32866 is a 1.8 V configurable register

1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications

SSTUB32865 1. General description The SSTUB32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two